Conventional data communication circuits require a precision timing component to provide a reference frequency clock signal to an external device that is coupled via a signal transmission bus to a host. A precision timing component in such communication circuits usually includes a crystal oscillation element. An internally based timer tunes the clock signal of the crystal oscillation element to match the clock signal to the incoming data stream from the host. Typically, a phase lock loop (PLL) or a delay lock loop (DLL) in the timer serves the functions of tuning and locking the clock signal through data training, phase shifting, phase selection, or the like. The crystal oscillator is expensive. The internally based timer typically requires long training sequences to tune a PLL or DLL, which may not be available in modern applications, such as universal serial bus (USB) applications.
An alternative approach for locking the clock signal to the incoming data stream includes generating a clock signal from a current-controlled oscillator (ICO) or a voltage-controlled oscillator (VCO), analyzing the rates of an incoming data stream in at least two periods to generate two or more control signals, and adjusting the frequency of the clock signal in response to the control signals. Adjusting the frequency of the clock signal operates in an analog mode and generally includes at least two steps: a coarse tuning step followed by a fine tuning step. The ICO or VCO is an application specific integrated circuit (ASIC) that takes a large chip area and thereby increases the cost of the communication circuit. The analog multiple step tuning process is slow and complicated. The performance of the analog tuning circuit is susceptible to process and temperature variations. Complicated processing and circuit schemes may be required to reduce the variations and improve the performance and reliability of the tuning process.
Accordingly, it would be advantageous to have a cost efficient system and a process for synchronizing a clock signal to a data signal. It is desirable for the system to be simple and silicon area efficient. It is also desirable for the synchronization process to be fast and reliable. It is of further advantages for the system and the process to be unsusceptible to variations in chip fabrication processes and operation conditions.